1. Technical Field
The present invention generally relates to a semiconductor technology, and more particularly, to a stacked semiconductor package and a method for manufacturing the same.
2. Related Art
In the semiconductor industry, packaging technologies for integrated circuits have been continuously been developed to satisfy the demands toward miniaturization and mounting reliability. In recent years, as miniaturization and higher performances are demanded in electric and electronic products, various stacking techniques have been developed.
The term “stack” as used in the semiconductor industry means to pile vertically two or more semiconductor chips or semiconductor packages. With these stacking technologies, a memory element may have a memory capacity two or more times greater than that obtainable through semiconductor integration process. Besides the increased memory capacity, the stacked semiconductor packages also have advantages in terms of mounting density and efficient utilization of a mounting area. For these reasons, research and development for stacked semiconductor packages have been accelerated.
As an example of a stacked semiconductor package, a structure has been introduced in which through electrodes are formed in semiconductor chips such that upper and lower semiconductor chips are physically and electrically connected with one another by the through electrodes. Typical process steps for manufacturing such stacked semiconductor package using the through electrodes are as follows:
Via holes are defined at respective semiconductor chips through an etching process in a wafer level, and through electrodes are formed by filling a copper layer in the via. Front bumps connected with the through electrodes are then formed on a front surface of a wafer. Thereafter, with a support substrate attached to the front surface of the wafer in order to prevent warpage and crack from generated in the wafer during a subsequent back grinding process, a back surface of the wafer is back ground to expose the through electrodes and back bumps are then formed over the through electrodes at the back surface of the wafer. After detaching the support substrate, the semiconductor chips of the wafer are individualized by sawing the wafer. Then, the individualized semiconductor chips are stacked such that front bumps of the upper semiconductor chip are bonded on the back bumps of the lower semiconductor chip by medium of solder balls, thereby forming a stacked semiconductor package.
The stacked semiconductor package using such through electrodes has an advantage in that high operation speed and miniaturization can be achieved since electrical connections are made through the through electrodes.
The conventional stacked semiconductor packages, however, have disadvantages in that costs for forming bumps and solder balls are incurred and in that the upper and lower semiconductor chips are not electrically connected when the bumps and solder balls are not in place. The conventional stacked semiconductor packages have further disadvantages of poor electrical reliability and properties, e.g. decreased signal transfer speed since the solder balls have a resistance larger than that of copper (Cu) which is used as material for through electrodes. Moreover, in the conventional stacked semiconductor packages, support substrate attaching process and support substrate detaching process are performed on the respective wafers in order to accomplish thinning of semiconductor chips. The substrate attaching process and support substrate detaching processes are expensive processes that require high costs. Therefore, the conventional stacked semiconductor packages have disadvantages in that high costs are incurred to perform these expensive processes on respective wafers. In addition, in the conventional stacked semiconductor packages, it is necessary to back grind the wafer as thinly as possible in order to improve ion gettering properties upon back grinding the wafer. However, thin back grinding may lower chip strength, which results in a problem in that chips may be damaged when handling thinned chips after the back grinding. Therefore, back grinding roughly on the wafer should be performed to prevent chip damage but it is difficult then to ensure the ion gettering properties discussed above.